A high throughput and a high resistance to error have been required for recent wireless communication systems. In order to meet such demands, various techniques including error correction processes such as turbo coding, LDPC (Low Density Parity Check) coding, and convolutional coding have been used in a variety of wireless communication systems, such as LTE (Long Term Evolution) and WiMax. Those error correction processes, particularly decoding algorithms, require a large amount of bit processing and many repetitional processes and, as a result, need a great amount of calculations. Therefore, various proposals have been presented so far with regard to dedicated hardware engines suitable for decoding algorithms. Use of those dedicated hardware engines can provide a high throughput and high capability of error correction as required.
However, each of those dedicated hardware engines deals with a single decoding method in order to achieve high performance requirements. Herein, it is assumed that those dedicated hardware engines which would be a key technology to a next-generation wireless communication system are used in a software radio apparatus required for a multi-standard wireless system. In this event, such engines suitable for all of error correction algorithms used in a required communication method should be installed individually. In such a case, the scale of the circuit becomes large as an increase of the number of those dedicated hardware engines and results in an influence on the scale of the entire system. Furthermore, multiple types of dedicated hardware engines should be developed on all such occasions or on demand. This causes an increase of development cost.
With regard to those problems, there has been proposed a programmable engine that deals with multiple types of error correction algorithms Form the viewpoint of achieving a high throughput as required, proposals have been made about the architecture of the programmable engine formed by a single processor having a high operating frequency (see Non-Patent Document 1) or a plurality of processors arranged in parallel (see Non-Patent Document 2). The latter method using a plurality of processors would be effective in a wireless communication system in terms of a reduction of the electrical power consumption.
As shown in FIG. 6, a programmable engine disclosed in Non-Patent Document 2 includes a plurality of memory banks 50a, 50b, and 50c, a plurality of error correction processing parts 52a, 52b, and 52c, and an interconnect part 51. The memory banks 50a-50c are connected to the error correction processing parts 52a-52c via the interconnect part 51. Multiple sets of data can simultaneously be read from or written in each of the memory banks 50a-50c. The engine having the above configuration as disclosed in Non-Patent Document 2 operates as follows.
It is assumed that each of the memory banks and the error correction processing parts is equal to N in number and that M words of data can simultaneously be read from or written in one of the memory banks. For the sake of brevity, FIG. 6 shows an example where N=3 and M=32. Input data for an error correction process are stored in the memory banks. A plurality of data that can simultaneously be accessed in one memory bank are referred to as a data row.
First, an operation for LDPC decoding will be described. Data rows are read from the memory banks 50a-50c. The read data rows are subjected to a predetermined amount of shift in barrel shifters 51a, 51b, and 51c which are connected to the memory banks 50a, 50b, and 50c, respectively. The amount of shift differs depending upon the type of LDPC coding. The shifted data rows are inputted to the error correction processing parts 52a, 52b, and 52c. When the data rows are inputted to the error correction processing parts 52a-52c, a program for LDPC decoding is executed in each of the error correction processing parts 52a-52c, so that one repetition cycle of the LDPC decoding process is performed. The resultant computation results are outputted to the interconnect part 51. In the interconnect part 51, the inputted data rows are subjected to a reverse shift operation that is reverse to the shift operation performed at the time of input, so that the order of the data rows is recovered to the original one. The data rows in the original order are written back to the memory banks. This sequence is repeated a predetermined number of times. Thus, LDPC decoding for one code is conducted.
Next, an operation for turbo decoding will be described. In the case of the turbo decoding, the interconnect part 51 is operated in a different manner between an even number one of repetitive times and an odd number one of the repetitive times. When the repetition times are even, data rows inputted from the memory banks 50a-50c are inputted to the error correction processing parts 52a-52c without any change of the order of the data. When the repetition times are odd, data rows inputted from the memory banks 50a-50c are subjected to interleaving processing by a cross bar 51d of the interconnect part 51 and are inputted to the error correction processing parts 52a-52c after the order of the data has been changed. When the data rows are thus inputted, a program for turbo decoding is executed in the error correction process, so that a turbo decoding process is performed. The resultant computation results are subjected to de-interleaving depending upon whether the repetition times are even or odd like in the case of the input of the data rows from the memory banks and then are written back to the memory banks. This sequence is repeated a predetermined number of times. Thus, turbo decoding is conducted.
As described above, Non-Patent Document 2 can perform typical error correction processes, including LDPC decoding and turbo decoding, by the use of the same architecture.
As shown in FIG. 6, however, it should be pointed out that the architecture of Non-Patent Document 2 has limited or fixed connections between memory banks and the error correction processing parts. When multiple types of error correction methods are to be processed, only one type of error correction methods can be processed during a single operation in Non-Patent Document 2. This shows that a plurality of error correction processes should be successively or sequentially performed. Accordingly, even if a single error correction method is processed in connection with a certain code length an error correction process cannot be performed simultaneously on different code lengths from the certain code length. A next-generation wireless communication system, particularly a base station, requires decoding processes for a plurality of users. Furthermore, it would be desirable to effectively process a plurality of error correction methods and a plurality of code lengths. In most of the existing wireless communication systems, different error correction processes are performed for different communication channels. Thus, it would be desirable also to process a plurality of error correction methods and a plurality of different code lengths at one time.